Micron DDR5 Memory Now Supporting 4th Gen AMD EPYC Genoa CPUs, Based on “Zen 4” Architecture
Press Release: Micron Technology, Inc., (Nasdaq: MU) today announced the availability of DDR5 memory for the data center that is validated for the new AMD EPYCTM 9004 Series processors. As modern servers pack more processing cores into CPUs, the memory bandwidth per CPU core has been decreasing. Micron DDR5 alleviates this bottleneck by providing higher bandwidth compared to previous generations, enabling increased reliability and scaling. The combination of 4th Gen AMD EPYC processors and Micron DDR5 delivers up to two times the memory bandwidth on the STREAM benchmark and up to two times performance improvement on select HPC workloads such as computational fluid dynamics (OpenFOAM), Weather Research and Forecasting (WRF) modeling and CP2K molecular dynamics. Micron’s new DDR5 SDRAM delivers a 1.5 times increase in data rates at 4800 MT/s when compared to DDR4 3200, and enables features like on-die ECC, Error Check and Scrub (ECS), and fault bounding for increased reliability in the data center while continuing to scale density. Additionally, Micron is providing flexible memory solutions capable of fueling the continued expansion of CPU cores for data-intensive workloads like AI, advanced analytics, and high-performance computing (HPC).
4th Gen AMD EPYC processors continue to raise the bar for workload performance in the modern data center while simultaneously delivering exceptional energy efficiency. 4th Gen AMD EPYC processors will transform our customers’ data center operations by accelerating time to value, driving the lower total cost of ownership, and helping enterprises to address their sustainability goals,” said Ram Peddibhotla, corporate vice president, of EPYC product management, AMD. Micron compared the performance of the STREAM benchmark on a single 4th Gen AMD EPYC processor system populated with Micron DDR5 at 4800 MT/s to a 3 rd Gen AMD EPYC processor system and Micron DDR4 at 3200 MT/s. With the 4th Gen AMD EPYC processor system, Micron achieved a peak memory bandwidth of 378 GB/s per socket compared to 189 GB/s with 3 rd Gen AMD EPYC processor system. This resulted in a two-times increase in system memory bandwidth. In partnership with AMD, Micron evaluated three HPC workloads (OpenFOAM, WRF, and CP2K) on 3rd Gen AMD EPYC processors with Micron DDR4 and 4th Gen AMD EPYC processors with Micron DDR5. The 4th Gen AMD EPYC processor platform with Micron DDR5 improved the performance of OpenFOAM by 2.4 times, WRF by 2.1 times, and CP2K by 2.03 times. Micron has played a pivotal role in JEDEC’s creation of DDR5 memory specifications and was one of the first to sample DDR5 to customers. Micron’s Technology Enablement Program (TEP), the first of its kind in the industry, gave system designers early access to key internal resources to assist their DDR5 validation and qualification processes. Micron is committed to partnering across the ecosystem and will continue to invest in our leadership technology and product roadmaps. Scott Tease, vice president of HPC & AI, Lenovo Infrastructure Solutions Group.
